Memory BIST (built in self test) is an important tool for testing memories (including finding/diagnosing and repairing defects within those memories). As more memory is integrated into chips, thorough BIST test and repair is a requirement in order to ensure reasonable product quality/reliability levels. Also, as the amount of memories per chip increases with each advancing technology node, the density of the memories also increases which in-turn raises the probability of detecting more fails. Due to the large amount of memory present in each chip, the number of fails detected are also significant.
Diagnostics is a process of extracting information about the failing address locations and failure scenarios. By analyzing this data, it is possible to understand the memory failure modes and improve the BIST patterns. This also helps a designer to allocate the redundancies more efficiently. All these efforts help improve the yields in each technology node.
The diagnostics process currently employed shifts the fail information serially to a tester. This process needs to be repeated for each fail and for every memory on the chip. This tends to be a tedious process and takes up a lot of tester time which is expensive. Hence, speeding up the diagnostics process improves the throughput of the tester significantly.
The BIST is usually run in 2 modes. The first mode is used to observe the fails and the second mode is used to shift out the observed fails on the DIAG pin. While running in the second mode, the BIST pauses at the observed FAIL address and shifts the data for ‘n’ clock cycles, which depends on the length of the diagnostics chain. Once the shift is complete, BIST resumes with normal operation until the next FAIL is detected. The bottleneck in the above method is that it tends to be a manual process. As it is necessary to observe the fails in the first pass, the user needs to program the BIST to select the failing memory and configure the BIST in pause mode and then correctly shift for ‘n’ cycles based on the memory configuration where the FAIL is detected.